As a Principal Engineer, you will be responsible for Synthesis Including
Design for Testability and Statistics Time Analysis (Signoff) for SoC and IP
Levels.
You will also be responsible for:

* RTL Synthesis including design partitioning, timing and power constraints – netlist.
* Digital DFT Insertion flow.
* STA (timing sign-off) for SoC and IP level.
* Back Annotation with APR/Layout owner.
* Debug of post Silicon failures root cause analysis.

We're looking for an experienced engineer, with a no giving up attitude,
motivated to fulfill his goals in the best possible way. You must also have
background in synthesis, STA and DFT.

You will be a better fit if you have:

* College degree in Electrical Engineering;
* At least 5 years of experience running large scale synthesis and static timing analysis in deep submicron design technologies;
* Experience with design flows utilizing Unix, Linux and Verilog / System Verilog;
* Knowledge and experience of working with Synopsis (DC, Prime Time and ICC) and Mentor as DFT tool;
* Excellent knowledge of working with IPs integration and related views (Lib, ATPGLib, CTL, UPF, or others);
* Experience with Multi Voltage. Multi Corner experience would be a plus;
* Sound programming skills and knowledge in scripting languages;
* Capable of assisting in determining methods and procedures to use on new projects and new design;
* Very good English language skills.

The post Principal Engineer – System on Chip Synthesis (f/m/div)* appeared first on TechMonster.

As a Principal ASIC Design Engineer you will define, design and verify digital
logic systems on ICs.
In your new role you will:

* Develop architecture, module interfaces, and design approaches.
* Convert customer and product requirements into detailed design goals to be used in implementation.
* Develop, assess and refine RTL design to target power, performance, area and timing goals.
* Support test-bench development and simulation for functional and performance verification
* Explore high performance strategies and validate that the RTL design meets targeted performance.
* Work with cross-functional engineering teams to implement and validate physical design on the aspects of timing, area, reliability, testability and power.

You are an experienced engineer with a great focus on quality and a process-
oriented mindset. Furthermore, you are able to be flexible even in a complex
working environment and your team orientation allows you to closely cooperate
with your colleagues, across boundaries.
You are best equipped for this role if you have:

* Bachelor's degree in Electrical Engineering.
* At least 6 years of relevant experience within the semiconductor industry.
* Thorough knowledge of chip architecture.
* Knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging tools.
* Knowledge of logic design principles along with timing and power implications.
* Understanding of low power design techniques.
* Understanding of high-performance techniques and trade-offs.
* Hands on experience in logic synthesis and integrating RTL driven logic into the full chip
* Experience with Design For Test concepts and flows.
* Fluency in English

The post Principal ASIC Design Engineer (f/m/div)* appeared first on TechMonster.