We make life easier, safer and greener – with technology that achieves more,
consumes less and is accessible to everyone. Microelectronics from Infineon is
the key to a better future. Efficient use of energy, environmentally-friendly
mobility and security in a connected world – we solve some of the most
critical challenges that our society faces while taking a conscientious
approach to the use of natural resources.
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As a Principal Engineer, you will be responsible for Synthesis Including
Design for Testability and Statistics Time Analysis (Signoff) for SoC and IP
Levels.
You will also be responsible for:
* RTL Synthesis including design partitioning, timing and power constraints – netlist.
* Digital DFT Insertion flow.
* STA (timing sign-off) for SoC and IP level.
* Back Annotation with APR/Layout owner.
* Debug of post Silicon failures root cause analysis.
We're looking for an experienced engineer, with a no giving up attitude,
motivated to fulfill his goals in the best possible way. You must also have
background in synthesis, STA and DFT.
You will be a better fit if you have:
* College degree in Electrical Engineering;
* At least 5 years of experience running large scale synthesis and static timing analysis in deep submicron design technologies;
* Experience with design flows utilizing Unix, Linux and Verilog / System Verilog;
* Knowledge and experience of working with Synopsis (DC, Prime Time and ICC) and Mentor as DFT tool;
* Excellent knowledge of working with IPs integration and related views (Lib, ATPGLib, CTL, UPF, or others);
* Experience with Multi Voltage. Multi Corner experience would be a plus;
* Sound programming skills and knowledge in scripting languages;
* Capable of assisting in determining methods and procedures to use on new projects and new design;
* Very good English language skills.
